The present invention relates generally to memory devices and, in particular, to forming memory cells, including patterning conducting polymer films.
The volume, use and complexity of computers and electronic devices are continually increasing. Computers consistently become more powerful and new and improved electronic devices are continually developed (e.g., digital audio players, video players). Additionally, the growth and use of digital media (e.g., digital audio, video, images, and the like) have further pushed development of these devices. Such growth and development has vastly increased the amount of information desired/required to be stored and maintained for computer and electronic devices.
Generally, information is stored and maintained in one or more of a number of types of storage devices. Storage devices include long term storage media such as, for example, hard disk drives, compact disk drives and corresponding media, digital video disk (DVD) drives, and the like. The long term storage media typically store larger amounts of information at a lower cost, but are slower than other types of storage devices. Storage devices also include memory devices which are often, but not always, short term storage media. Short term memory devices tend to be substantially faster than long term storage media. Such short term memory devices include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), double data rate memory (DDR), fast page mode dynamic random access memory (FPMDRAM), extended data-out dynamic random access memory (EDODRAM), synchronous dynamic random access memory (SDRAM), VideoRAM (VRAM), flash memory, read only memory (ROM), and the like.
Memory devices can be subdivided into volatile and non-volatile types. Volatile memory devices generally lose their information if they lose power and typically require periodic refresh cycles to maintain their information. Volatile memory devices include, for example, random access memory (RAM), DRAM, SRAM and the like. Non-volatile memory devices maintain their information whether or not power is maintained to the devices. Non-volatile memory devices include, but are not limited to, ROM, programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash EEPROM and the like. Volatile memory devices generally provide faster operation at a lower cost as compared to non-volatile memory devices.
Memory devices generally include arrays of memory cells. Each memory cell can be accessed or xe2x80x9creadxe2x80x9d, xe2x80x9cwrittenxe2x80x9d, and xe2x80x9cerasedxe2x80x9d with information. The memory cells maintain information in an xe2x80x9coffxe2x80x9d or an xe2x80x9conxe2x80x9d state, also referred to as xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d. Typically, a memory device is addressed to retrieve a specified number of byte(s) (e.g., 8 memory cells per byte). For volatile memory devices, the memory cells must be periodically xe2x80x9crefreshedxe2x80x9d in order to maintain their state. Such memory devices are usually fabricated from semiconductor devices that perform these various functions and are capable of switching and maintaining the two states. A common semiconductor device employed in memory devices is the metal oxide semiconductor field effect transistor (MOSFET).
The use of portable computer and electronic devices has greatly increased demand for memory devices. Digital cameras, digital audio players, personal digital assistants, and the like generally seek to employ large capacity memory devices (e.g., flash memory, smart media, compact flash, . . . ). The increased demand for information storage is commensurate with memory devices having an ever increasing storage capacity (e.g., increase storage per die or chip). A postage-stamp-sized piece of silicon may, for example, contain tens of millions of transistors, each transistor as small as a few hundred nanometers. However, silicon-based devices are approaching their fundamental physical size limits. Inorganic solid state devices arc generally encumbered with a complex architecture which leads to high cost and a loss of data storage density. The volatile semiconductor memories based on inorganic semiconductor material must constantly be supplied with electric current with a resulting heating and high electric power consumption in order to maintain stored information. Non-volatile semiconductor devices have a reduced data rate and relatively high power consumption and large degree of complexity.
Moreover, as the size of inorganic solid state devices decreases and integration increases, sensitivity to alignment tolerances increases making fabrication markedly more difficult. Formation of features at small minimum sizes does not imply that the minimum size can be used for fabrication of working circuits. It is necessary to have alignment tolerances which are much smaller than the small minimum size, for example, one quarter the minimum size.
Scaling inorganic solid state devices raises issues with dopant diffusion lengths. As dimensions are reduced, the dopant diffusion lengths in silicon are posing difficulties in process design. In this connection, many accommodations are made to reduce dopant mobility and to reduce time at high temperatures. However, it is not clear that such accommodations can be continued indefinitely.
Applying a voltage across a semiconductor junction (in the reverse-bias direction) creates a depletion region around the junction. The width of the depletion region depends on the doping levels of the semiconductor. If the depletion region spreads to contact another depletion region, punch-through or uncontrolled current flow, may occur.
Higher doping levels tend to minimize the separations required to prevent punch-through. However, if the voltage change per unit distance is large, further difficulties are created in that a large voltage change per unit distance implies that the magnitude of the electric field is large. An electron traversing such a sharp gradient may be accelerated to an energy level significantly higher than the minimum conduction band energy. Such an electron is known as a hot electron, and may be sufficiently energetic to pass through an insulator, leading to irreversibly degradation of a semiconductor device.
Scaling and integration makes isolation in a monolithic semiconductor substrate more challenging. In particular, lateral isolation of devices from each other is difficult in some situations. Another difficulty is leakage current scaling. Yet another difficulty is presented by the diffusion of carriers within the substrate; that is free carriers can diffuse over many tens of microns and neutralize a stored charge. Thus, further device shrinking and density increasing may be limited for inorganic memory devices. Furthermore, such device shrinkage for inorganic non-volatile memory devices while meeting increased performance demands is particularly difficult, especially while maintaining low costs.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its purpose is merely to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
In accordance with one or more aspects of the present invention, a methodology for forming a memory cell is disclosed. The memory cell is formed on a conductive layer, such as copper, that can serve as a bitline for, among other things, addressing the memory cell. A polymer layer is formed over the conductive layer and an electrode layer is formed over the polymer layer. An antireflective coating can optionally be formed over the electrode layer to alter the reflectivity of the stack. A first via is then etched into the antireflective, electrode and polymer layers, and a dielectric material is applied over the stack to at least fill in the first via. A second via is then etched into the dielectric material so as to expose and make the electrode layer available as a top electrode. Finally, a wordline is formed over the dielectric material such that the top electrode is connected to the wordline by way of the second via.
According to one or more further aspects of the present invention, the method can also include forming a photoresist layer over the antireflective coating, forming a pattern into the photoresist layer, developing the photoresist layer and utilizing the developed photoresist as a mask for etching the first via. The undeveloped portions of the photoresist layer can be removed as the first via is etched into the polymer layer.
According to one or more additional aspects of the present invention, a memory device formed in accordance with a disclosed process includes a top electrode formed over a polymer layer, a conductive layer under the polymer layer, a via defined by a dielectric material and located above the top electrode, and a wordline over the dielectric material such that the top electrode is connected to the wordline by way of the via.
To the accomplishment of the foregoing and related ends, certain illustrative aspects of the invention are described herein in connection with the following description and the drawings. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed, and the present invention is intended to include all such aspects and their equivalents. It is to be appreciated that other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.